Tech FAQ

No, when using the asynchronous mode of communication, a half duplex UART will not work. The host must be ready to receive messages from ANT at any point.

If the use of an external 32 KHz crystal input is desired, the message of ANT_CrystalEnable(0) must be sent once, each time a start up message is received.

You can find more details by reading through the "Getting Started with ANT Development in Embedded Systems" thread and particularly the "AN13 Power States" application note. These documents may be found here .

For the UART interface, using the SLEEP line appropriately, would let you reopen channels without having to go through the entire configuration. The Sleep pin in UART tells ANT it can turn off the serial port when it is unneeded thus saving power.
In SPI state transitions are generally automatic except for AP2's "Deep Sleep" which is also available on the UART.

However, AP2 does offer a "Deep Sleep" state designed for long durations between activity as it causes a full reset of the AP2, but in this mode AP2 will only draw ~0.5uA. That state is entered through a command specific to the AP2.

Yes – a HW SPI SPI hardware will work well with ANT in byte synchronous mode. ANT is the master in the link. The MOSI, MISO and SCLK lines of the SPI port can be interfaced to SOUT, SIN and SCLK directly. The SS line of a traditional SPI port should NOT be used. Although similar in functionality to SEN, this control signal works a little differently in the ANT implementation and should be implemented using a GPIO. Other control lines should also be implemented using GPIO’s.

Please refer to Interfacing with ANT General Purpose Chipsets and Modules for details. These documents may be found here.

The System Reset command does a software reset of the system, jumping to the reset vector.

No. Although ANT supports the SPI protocol, it implements extra flow control lines that make it incompatible with a DMA. These extra control lines must be controlled by software and GPIOs.

The RESET command resets the ANT baseband processor; hence ANT is not able to respond. A delay of at least 500ms should be added after a reset command is sent to ANT.

Yes. Due to the resource constraints of the ANT baseband processor, there is very little space to buffer bytes received from the host MCU. To ensure packets are not dropped, flow control must be implemented properly. This is especially important if doing burst transfers.

Bit and Byte synchronous differ in the flow control mechanism of the serial port. Byte synchronous requires that the host MCU toggle its SRDY line before an entire byte (8-bits) is sent or received by ANT. Bit synchronous requires that the host MCU toggle its SRDY line before each bit is clocked by ANT. That is, ANT will not generate a clock transition unless it detects an SRDY falling edge. Byte synchronous is most appropriate if using a hardware SPI module in the host MCU. Bit synchronous should be used if there is no hardware support for either synchronous or asynchronous serial communication on the host MCU and the entire interface must be implemented in software using GPIOs. This is also known as “bit-bashing”.

ANT chipsets and modules  support a serial communication interface. There are two options available: asynchronous (UART) and synchronous (SPI). There are two flavors of the synchronous interface – byte synchronous and bit synchronous. Both serial interfaces implement a simple serial message protocol that enables the user to utilize the full capacity of ANT. 

For details on the hardware interface, please refer to Interfacing with ANT General Purpose Chipsets and Modules. For details on the messaging protocol, please refer to ANT Message Protocol and Usage. These documents may be found here .

Yes. The bit synchronous serial interface allows a host MCU to implement a software interface using the general purpose I/O lines on the MCU. This is also known as “bit-bashing”.

Once the synchronous reset is complete, ANT is in a state to receive a message from the host MCU. It is not possible to change this state. It is recommended that the System Reset command can then be sent following a synchronous reset.

Reference source code is available to registered members on the downloads page. In order to view ANT source code, you will need to become an ANT+ Adopter which is free of charge. Please refer to the ANT Licensing section for more details.

The latest version of the ANT Network Processor can be found in the N5 Starter Kit SDK on the Downloads page.

The N5 module supports up to 15 ANT channels. This must be configured before initializing the S210/S310 SoftDevice.

ANT in new devices such as the nRF52 now offers the ability to transmit precise timing data over bi-directional channels using the Time Sync feature, enabling multiple devices to synchronize timing to any given source. For more information on Time Sync, the application note can be found here.