- THIS IS ANT

Username		Password		Remember Me?	forgot password?

05 December 2011 11:48 PM

hku_arch Newbie

Total Posts: 6

Joined 2011-03-08

Hi,

I am having some occasional problems with the sync enable signal between my host MCU and ANT while bursting.
Once in a while, it seems that the sync enable signal never deasserts itself while bursting. Do you know what would cause this to occur? Please see my attached scope outputs. At the end of the timeline, sync_enable never deasserts and ends up locking up my MCU.

Thank you for your help.

Harvey

06 December 2011 10:02 AM #1

alejandra Moderator

Total Posts: 662

Joined 2012-10-09

PM

Reposting image... [img size=800]http://www.thisisant.com/images/fbfiles/images/scope_0_sm.jpg[/img]

06 December 2011 10:07 AM #2

alejandra Moderator

Total Posts: 662

Joined 2012-10-09

PM

Can we obtain a close up of the last two packets?

06 December 2011 03:42 PM #3

hku_arch Newbie

Total Posts: 6

Joined 2011-03-08

PM

Hi Alejanda,

Please see attached image of close up.

Thank You,
Harvey [img size=820]http://www.thisisant.com/images/fbfiles/images/scope_1.jpg[/img]

06 December 2011 04:26 PM #4

alejandra Moderator

Total Posts: 662

Joined 2012-10-09

PM

The close up diagram shows two bytes being transmitted to ANT, however, there does not seem an SRDY pulse in between them. Can you get a better picture that includes both of these two packets coming out entirely. Specifically, we'd like to see the SRDY pulse prior to the second to last byte, there, and whether there are two SRDY toggles there.

06 December 2011 04:40 PM #5

hku_arch Newbie

Total Posts: 6

Joined 2011-03-08

PM

Hi Alejandra,

I think I see the problem that you are referring to with the SRDY signal. Please see attached.

Thank You,
Harvey [img size=820]http://www.thisisant.com/images/fbfiles/images/scope_2.jpg[/img]

06 December 2011 05:25 PM #6

alejandra Moderator

Total Posts: 662

Joined 2012-10-09

PM

I would recommend looking into your implementation of SRDY, specifically
- Why is SRDY being pulsed in the middle of a byte TX?
- Why is the last SRDY pulse so long?

From this last diagram, ANT is receiving only 4 bytes, instead of a full burst packet, and that is why SEN does not get deasserted.

07 December 2011 03:08 AM #7

Johnny Ringo Sr. Member

Total Posts: 523

Joined 2012-11-15

PM

Hi Alejandra,

I've found the problem, apparently my SRDY signal was being interrupted with another process randomly from our RTOS. By adding in critical sections, the crashing has stopped.

Thanks for the tips!

Harvey

ANT Forum

problem with sync enable