ANT Forum

I'm trying to use a ANTAP281M5IB module with an AVR processor SPI interface. From the ANT interfacing document I've been trying to implement the synchronous reset, I've attached a pdf of a timing diagram showing precisely what I'm doing. After asserting the /SRDY and /SMSGRDY as shown I expected the SEN line to be high and then go low. My interpretation was that I should then reset /SRDY. In fact what happens is that /SEN is low after power up and goes high on the rising edge of /SRDY as I've sketched in the second pdf and stays high.

I wondered if I had misinterpreted the sequence so I tried to start a transfer sequence by asserting /SMSGRDY and pulsing /SRDY but /SEN remains high.

I'm rather in the dark about what the actual timing of any of these signal should be other than the actual reset period being >250 us.

I'm obviously doing something wrong and some help would be very much appreciated.
[file name=ANT_observed_reset_timing.pdf size=16288]http://www.thisisant.com/images/fbfiles/files/ANT_observed_reset_timing.pdf[/file]      

I'm trying to use a ANTAP281M5IB module with an AVR processor SPI interface. From the ANT interfacing document I've been trying to implement the synchronous reset, I've attached a pdf of a timing diagram showing precisely what I'm doing. After asserting the /SRDY and /SMSGRDY as shown I expected the SEN line to be high and then go low. My interpretation was that I should then reset /SRDY. In fact what happens is that /SEN is low after power up and goes high on the rising edge of /SRDY as I've sketched in the second pdf and stays high.

I wondered if I had misinterpreted the sequence so I tried to start a transfer sequence by asserting /SMSGRDY and pulsing /SRDY but /SEN remains high.

I'm rather in the dark about what the actual timing of any of these signal should be other than the actual reset period being >250 us.

I'm obviously doing something wrong and some help would be very much appreciated. [img size=800]http://www.thisisant.com/images/fbfiles/images/AVR_ANT_reset_timing_copy.jpg[/img]      

A quick update

I found the Reference Design User Manual (D00001087) with detailed instructions for the Synchronous Reset Sequence and implemented them exactly. I still can't get any life from /SEN.      

How long do you wait before you set Reset to low after reset an how long do you wait with the first message after you set Reset to high?

Check this out (I had the same problems):
http://www.thisisant.com/component/option,com_fireboard/Itemid,146/id,1570/catid,25/func,fb_pdf/

BTW: I used a Xmega to communicate with the AP2. I believe that you can only write into the SPI Data Register when the the SS Pin is high. So you have to observe the SS Pin by an extra I/O.      

Hi,

The AP2 supports a hard reset pin, have you tried utilizing that line to ensure the AP2 is operating correctly?

At startup I would recommend waiting at least 1 ms before attempting to reset.

Did you see any activity on the SCLK or SOUT lines? From first glance it appears the AP2 was attempting to send the sync byte.

Best regards,
Harrison