Commonly, when connect MCU and ANT in SPI mode, four logic signal necessary.
The SPI bus specifies four logic signals:
SCLK: serial clock (output from master);
MOSI: master output, slave input (output from master);
MISO: master input, slave output (output from slave);
SS: slave select (active low, output from master).
In the "Interfacing with ANT General Purpose Chipsets and Modules" document there is diagram concering Synchronous serial interface.
Specially ANT use 6 pin on the sync. serial interface.
/SRDY, SIN, SOUT, SCLK, /SEN, /SMSGRDY
Then /SRDY pin is SS(slave select) pin?
