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Ant_Reset_ResetPin()). After reset I successfully read first message sent from the Ant module. The message has 5 bytes but its content is invalid. First of all, I'll describe my setup.CKP = 1, meaning "Idle state for clock is a high level; active state is a low level", and CKE = 0, meaning "Transmit happens on transition from Idle clock state to active clock state". On board reset, I receive the following from the Ant module:
ANT reset
ANT->HOST: 12
ANT->HOST: c0
ANT->HOST: 7b
ANT->HOST: 40
ANT->HOST: 69
CKE SPI setting so I tried with 1 too with the following result:
ANT->HOST: 49
ANT->HOST: 20
ANT->HOST: 3d
ANT->HOST: a0
ANT->HOST: 74
0xA4, the length isn't 1 and the checksum is invalid. What could be my problem?
#include <xc.h>
#include <stdint.h>
#include <stdio.h>
#define FOSC 3686400
#define FCY (FOSC/2)
#include <libpic30.h>
#pragma config JTAGEN = OFF
#pragma config GWRP = OFF
#pragma config FWDTEN = OFF
#pragma config ICS = PGx3
#pragma config FWPSA = PR128
#pragma config WDTPS = PS2048
#pragma config FCKSM = CSECMD
#pragma config OSCIOFCN = OFF
#pragma config POSCMOD = XT
#pragma config FNOSC = PRI
#define IO_TRIS_SPI_SDO _TRISG7
#define IO_PORT_SPI_SDO _RG7
#define IO_LAT_SPI_SDO _LATG7
#define IO_TRIS_SPI_SCK _TRISG8
#define IO_PORT_SPI_SCK _RG8
#define IO_LAT_SPI_SCK _LATG8
#define IO_TRIS_SPI_SDI _TRISB4
#define IO_PORT_SPI_SDI _RB4
#define IO_LAT_SPI_SDI _LATB4
#define IO_TRIS_ANTRFID_nRESET _TRISA4
#define IO_PORT_ANTRFID_nRESET _RA4
#define IO_LAT_ANTRFID_nRESET _LATA4
#define IO_TRIS_ANT_nSRDY _TRISF4
#define IO_PORT_ANT_nSRDY _RF4
#define IO_LAT_ANT_nSRDY _LATF4
#define IO_TRIS_ANT_nMRDY _TRISF5
#define IO_PORT_ANT_nMRDY _RF5
#define IO_LAT_ANT_nMRDY _LATF5
#define IO_TRIS_ANT_SFLOW _TRISE0
#define IO_PORT_ANT_SFLOW _RE0
#define IO_LAT_ANT_SFLOW _LATE0
#define IO_TRIS_ANT_SEN _TRISE1
#define IO_PORT_ANT_SEN _RE1
#define IO_LAT_ANT_SEN _LATE1
static void SPI_Init(void)
{
_SPI1TXIE = 0; // disable receive interrupts
SPI1CON1Lbits.SPIEN = 0; // stop and reset SPI
/*
* pin 11 ~ RP26 ~ RG7 ~ SDO
* pin 21 ~ RP21 ~ RB4 ~ SDI
* pin 12 ~ RP19 ~ RG8 ~ SCK
*/
IO_TRIS_SPI_SDO = 0;
IO_TRIS_SPI_SDI = 1;
IO_TRIS_SPI_SCK = 1;
_RP26R = _RPOUT_SDO1;
_SDI1R = 21;
_SCK1R = 19;
SPI1CON1Lbits.MSTEN = 0; // slave mode
SPI1CON1Lbits.ENHBUF = 0; // single byte buffer
SPI1CON1Lbits.CKP = 1; // clock polarity (idle is 1, active is 0)
SPI1CON1Lbits.CKE = 0; // clock edge (tx happens on falling edge, probably...)
while (SPI1STATLbits.SPIRBF) { // clear the receive buffer
(void) SPI1BUFL;
(void) SPI1BUFH;
}
(void) SPI1STATLbits.SPIROV; // clear the RX overflow flag
SPI1CON1Lbits.SPIEN = 1; // enable the SPI module
}
uint8_t SPI_TransferBlocking(uint8_t b)
{
SPI1BUFL = b;
while (!SPI1STATLbits.SPIRBF);
return SPI1BUFL;
}
void ANT_InitPins(void)
{
IO_TRIS_ANTRFID_nRESET = 0;
IO_TRIS_ANT_nMRDY = 0;
IO_TRIS_ANT_nSRDY = 0;
IO_TRIS_ANT_SFLOW = 0;
IO_TRIS_ANT_SEN = 1;
IO_LAT_ANTRFID_nRESET = 1;
IO_LAT_ANT_SFLOW = 0;
IO_LAT_ANT_nMRDY = 1;
IO_LAT_ANT_nSRDY = 1;
}
void ANT_Reset_ResetPin(void)
{
IO_LAT_ANTRFID_nRESET = 0;
__delay_ms(1);
IO_LAT_ANTRFID_nRESET = 1;
__delay_ms(1);
}
void InitUART(void);
int main(void)
{
// make all pins digital
ANSA = ANSB = ANSC = ANSD = ANSE = ANSF = ANSG = ANSH = 0;
InitUART();
SPI_Init();
ANT_InitPins();
ANT_Reset_ResetPin();
printf("ANT reset\r\n");
__delay_ms(1000);
while (1) {
if (!IO_PORT_ANT_SEN) {
IO_LAT_ANT_nSRDY = 0;
__delay_us(50);
IO_LAT_ANT_nSRDY = 1;
uint8_t b = SPI_TransferBlocking(0);
printf("ANT->HOST: %x\r\n", b);
}
}
return 0;
}
#define UART_BAUDRATE 115200
void InitUART(void)
{
_U1TXIE = 0;
_U1RXIE = 0;
_RP11R = _RPOUT_U1TX;
_U1RXR = 12;
U1MODEbits.STSEL = 0;
U1MODEbits.PDSEL = 0;
U1MODEbits.ABAUD = 0;
U1MODEbits.BRGH = 0;
U1BRG = (int) (FCY/(16 * UART_BAUDRATE) - 1);
U1MODEbits.UARTEN = 1;
U1STAbits.UTXEN = 1;
__delay_ms(1000000/UART_BAUDRATE);
}
void putch(unsigned char ch)
{
while (U1STAbits.UTXBF);
U1TXREG = ch;
__delay_ms(1); // FIXME
}
