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difficulty in communicating with the nRF24AP1 Synchronous serial interface

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From a valued customer, Frank Mancuso


Hello, I am having difficulty in communicating with the nRF24AP1 Synchronous serial interface.

The nRF2AP1 seems to be responding to the Host -> ANT transactions but it does not respond back. The nRF24AP1 generates a clock signal when I enable the SMSGRDY signal (SMSGRDY = 0) so this is why I assume the nRF24AP1 is functional.

By the way the timing diagram in the 'Interfacing with ANT General Purpose Chipsets and Modules' document D00000794 Rev 1.3 suggests that the /SMSGRDY signal should be active for the first byte (page 13, Figure 3-5: Host -> ANT Transaction (Software SRDY ) but this is not true. I have to keep this signal active for the entire message otherwise the nRF24AP1 will not generate the clock when I raise the /SMSGRDY signal.

Here is a description of the microprocessor firmware communications with the nRF24AP1

Powerup and message sequence

1. On powerup the microprocessor enables the /SRDY signal (/SRDY =0) waits 500uS and then enables SMSGRDY (/SMSGRDAY = 0).

2. Both signals are then deactivated (/SRDY and /SMSGRDY = 1)


Microprocessor sends Assign Channel Command (0xA5,0x03,0x42,0x00,0x10,0x00,0xF4)

3. microprocessor enables /SMSGRDY (/SMSGRDY = 0)

4. nRF24AP1 responds by enabling /SEN (/SEN = 0)

5. microprocessor generates a pulse on /SRDY (~ 500 uS active low pulse)

6. nRF24AP1 generates the clock signal and sends byte 0xA5 on nRF24AP1 DOUT signal indicating it is a Host -> ANT transaction

7. microprocessor proceeds to generate a pulse on /SRDY (500 uS active low pulse)

8. nRF24AP1 generates the clock signal for the microprocessor to send the data to the nRF24AP1 DIN pin

9. microprocessor sends the "Assign Channel Command" bytes above on the nRF24AP1 DIN pin

10. steps 7-9 are performed until all bytes are read by the nRF24AP1.

11. microprocessor raises the /SMSGRDY signal

PROBLEM
After the sequence above the nRF24AP1 never responds to the "Assign Channel Command". I never see it lower the /SEN line as indicated in the timing diagrams or generate the clock signal when the micro pulses the /SRDY line.

It appears the nRF24AP1 is communicating since it generates the clock signal however I can't get it to respond to commands. I am sending the data with LSB first as indicated in the documentation and I have checked this with an oscilloscope.

Please provide insight into this matter. More detailed information is appreciated including software examples. The D00000794 Rev 1.3 document is not very clear in describing the serial synchronous interface.

Thank you for your assistance.      
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From what you describe, it seems that you are not getting proper synchronization with ANT after power up. Please make sure to apply the reset sequence described in Fig. 3.9 of the "Interfacing with ANT General Purpose Chipsets and Modules" document.

You should wait for the system to come up properly after power up before attempting the reset sequence (~1 ms).

SRDY and SMSGRDY should be high initially. Pull SRDY low, wait at least 250us, and then pull SMSGRDY low. You should then wait for a high to low transition on SEN to start pulsing SRDY to get ANT to generate the clock for transmission of the first message. If you do not see the high to low transition of SEN within ~1ms of applying the reset sequence, you should attempt the reset again.

After the reset sequence, the best practice is to send the system reset command (0x4A).      
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"SRDY and SMSGRDY should be high initially. Pull SRDY low, wait at least 250us, and then pull SMSGRDY low. You should then wait for a high to low transition on SEN to start pulsing SRDY to get ANT to generate the clock for transmission of the first message"

I do watch a high to low transition on SEN. But, ANT chip doesn't generate the clock.I only watch it generated a single low pulse before pulling up the SRDY. very confused!
I just did it according to timing figure gaven in the document.

Please help me.Thank you.




alejandra wrote:
From what you describe, it seems that you are not getting proper synchronization with ANT after power up. Please make sure to apply the reset sequence described in Fig. 3.9 of the "Interfacing with ANT General Purpose Chipsets and Modules" document.

You should wait for the system to come up properly after power up before attempting the reset sequence (~1 ms).

SRDY and SMSGRDY should be high initially. Pull SRDY low, wait at least 250us, and then pull SMSGRDY low. You should then wait for a high to low transition on SEN to start pulsing SRDY to get ANT to generate the clock for transmission of the first message. If you do not see the high to low transition of SEN within ~1ms of applying the reset sequence, you should attempt the reset again.

After the reset sequence, the best practice is to send the system reset command (0x4A).
     
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Could you describe in detail the sequence you are doing since power up?      
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Last time, I made a mistake between SRDY and SMSGRDY.
Now, another question.
After synchronization with ANT after power up, it generates SCLK out. I can read the byte "0xA5",sent from it.Then I send the "reset" command to it. After sending command, SEN is still low.
How does signal SEN change? What does it change according to?The document is not very clear about this.
help me, thanks.      
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SEN will pulse after the synchronous reset sequence, but not necessarily after sending a command (such as the reset command). When SEN is high, it means that ANT is not ready to send/receive serial messages - it provides flow control.

Right after the reset command, ANT should be ready to receive messages from the host. Wait ~500ms after the command for the reset to be completed, and you should be able to start sending other commands.