ANT Forum

Hi, everyone, I have got some problem in using atmega162 MCU to communicate with nRF24AP1 by Synchronous Serial Interface. I need help on it.

Acturally, if I pull down the SMSGRDY signal (SMSGRDY=0), the MCU can read the '0xA5' sync byte, and on each SRDY down pulse I can see the clock signal from AP1, but if I failed to set SMSGRDY 0, I can't read anything from AP1, so I can't get any response from AP1 after I send a message, I have no idea of this problem.

thanks for your help, I do appreciate it!      

Can you please describe in detail your reset sequence, from power up until you attempt to send/receive the first message from ANT? What do you see in SEN?      

thanks for your attention!

Upon power up,the detailed reset sequence is:

CONFIG_DIR_SYN; ///configure the i/o directions
SET_PORTSEL_1; ///select Synchronous serials interface,
SET_SFLOW_0; ///select Byte mode,SFLOW=0
SET_SMSGRDY_1; ///initial SMSGRDY=1
SET_SRDY_1; ///initial SRDY=1
_delay_ms(3);
///reset sequence begin
SET_SRDY_0; ///SRDY=0
_delay_ms(1); ///delay for 1ms
SET_SMSGRDY_0; ///SMSGRDY=0
while(!GET_SEN){;} ///wait til SEN=1
while(GET_SEN){;} ///wait til SEN=0

_delay_ms(1);
SET_SRDY_1; ///SRDY=1
SET_SMSGRDY_1; ///SMSGRDY=1
_delay_us(1);





after this sequence, I begin to read the first byte from AP1,the read sequence is:

///down pulse the SRDY
SET_SRDY_0; ///SRDY=0
SET_SRDY_1; ///SRDY=1

///#define GET_SOUT ((1<<2)&pin11;)
while((GET_SCLK)){;} ///wait til SCLK=0
while(!(GET_SCLK)){;} ///wait til SCLK=1
temp1[0]=GET_SOUT; ///read the first bit

while((GET_SCLK)){;}
while(!(GET_SCLK)){;}
temp1[1]=GET_SOUT;
.........

the first byte I get from AP1 was 165(0xA5),

another strange thing was that I have to down pulse SRDY several more times after sending all bytes in one message to make sure I can get '0xA5' to start another message sending. I was really confused!

thank you very very much,alejandra      

Make sure you wait after power up for the system to come up before attempting the reset sequence (~1ms).

From the snippet posted, it looks like you are polling for SCLK to read each bit - there is a chance you might be missing clock pulses, throwing off your synchronization. It seems you are implementing your serial interface on software, is this right? Bit synchronous communication would be a better option in this case. If you do have a hardware interface available (I believe the Atmega162 has both UART and SPI), using it might be a better choice, as you would not have to handle the timing in software.      

thank you alejandra!
I have try the bit synchronous communication and wait more than 1ms upon power up for the system to come up, but it behaved the same. I will have a try using hardware spi to communicate with ANT, I really don't know whether it could work normal.      

Hi,alejandra,
when I was using the MCU's SPI hardware interface to communicate with the ANT single chip, the SCLK and SOUT signal phase were not as described in the document "interfacing with ant general purpose chipsets and modules", and I found that the SOUT signal seemed half circle late than normal phase. If I sample the SOUT at the rising edge of SCLK signal, I will get '0xEF' instead of the synchronous byte '0xA5', but if I sample the data at the second falling edge of SCLK signal, I will get a 7bits binary data 0100101, just 1bit less than '0xA5' (10100101).
I have watch the wave form of the two pin,SCLK and SOUT, and found my guess was right, SOUT was half circle late than normal.I don't know how could it happen.
Thanks!alejandra      

Hi Qin,

In byte synchronous mode, data is transmitted LSB first and should be read on the rising edge of SCLK. Many SPI hardware implementations are configurable; make sure your SPI is set to meet these requirements from ANT.

If you still see this odd behavior, please post a scope trace of your sync reset, as well as the transmission of the synch byte.