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22 February 2010 12:14 PM

Johnny Ringo Sr. Member

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Joined 2012-11-15

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Hi everybody,

I'm trying to implement a 'Bit Synchronous' serial interface. I'm using the state machine found in the doc: "ANT Reference Design User Manual".

During the serial lines initialization and synchronous reset sequence state, SEN has the same waveform than describe in "interfacing with ant general purpose ... " document, but SCLK goes from high to low state and stay low as soon as MGRDY and SRDY are asserted. So I can't read the SYNC byte.

Does somebody have an idea why it goes that way?

08 March 2010 03:16 PM #1

alejandra Moderator

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Joined 2012-10-09

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Could you describe in detail the sequence you perform from power up until sending the first ANT message?
Please make sure to wait ~1ms after power up to allow the system to come up before attempting the synchronous reset.

29 March 2010 02:14 PM #2

Johnny Ringo Sr. Member

Total Posts: 523

Joined 2012-11-15

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Hi,

I'm using a state machine to control my transaction.

1st step: SMSGRDY = '1' and SRDY = '1' for 1 ms,
2nd step: SMSGRDY = '1' and SRDY = '0' for 300 us,
3rd step: SMSGRDY = '0' and SRDY = '0' for 1 ms,
4th step: SMSGRDY = '0' and SRDY = '1', if SEN = '0' then I start my transmission, else I restart this 4 steps. I my case, SEN goes low, but at this point I should have SCLK = '1' or SCLK = '0'.

After, when I want to transmit I wait that SEN = '0', if ok, I generate a 1ms pulse on SRDY, if after 30 us SEN is still high I put SMSGRDY high for 3 us en try to restart my transmission.

Do you see a problem in my state machine?

Regards,
Lionel.

30 March 2010 09:43 AM #3

alejandra Moderator

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Joined 2012-10-09

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Are you using bit or byte synchronous communication?

You should wait 1ms before #1, to give the system enough time to come up after power up.
The sequence for your synchronous reset looks OK, except by #4.
After the reset, you should be looking for a transition of SEN from high to low before you start pulsing SRDY, not the other way around.

During normal message transmissions, pulsing SRDY for 1ms seems rather long, the minimum SRDY low time is 2.5us. Note that when you want to initiate a transmission to ANT, you must assert SMSGRDY first to enter into transmit mode, and that you should be looking at SEN first before pulsing SRDY. Make sure to always look at the sync byte to identify if ANT is trying to send the host a message, or if you can go ahead and send a message to ANT.

31 March 2010 06:53 AM #4

lgautier Newbie

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Joined 2010-01-29

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Hi,

I've change my state machine (cf: file attached) but SEN stay low.
I've put a pull-up resistance on the SEN line.

I'm using bit synchronous communication, but for now I'm just trying to read the SYNC byte.

I really don't understand where my problem comes from, do you have any ideas?

Regards, Lionel. [img size=550]http://www.thisisant.com/images/fbfiles/images/state_machine_SSI.png[/img]

01 April 2010 09:05 AM #5

alejandra Moderator

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Since the ANT part you are using has a RST line, you can use this instead of the synchronous reset sequence. Doing two resets should still work, but it is not necessary.

When does SEN stay low? Do you have any scope captures of the sequence that leads to this?

At the end of your state machine (PULSE_SRDY2), SRDY is being asserted before reading the sync byte. After you pulse SRDY (low, then high), you should see clock pulses being generated. Do you see this? After you receive the sync byte, you can pulse SRDY again to proceed with the next byte.

01 April 2010 09:49 AM #6

lgautier Newbie

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I'm using the Figure 3-2 "Synchronisation with ANT upon start-up" of the document "Interfacing with ant general purpose chipsets and modules".
In this document it seems that SRDY must be assert to generate SCLK.

On the same figure, I don't really understand the meaning of the spire between SEN and SRDY after the reset sequence.

Finally, I'm using the battery board to communicate with the ANT chip. Maybe I've problem with SEN due to the configuration of my switch. I've tied SFLOW and PORTSEL (pins 2 and 3) to High, but what do I have to do with IOSEL, BR2 and BR3 (pins 1, 4 and 5)?

01 April 2010 10:55 AM #7

alejandra Moderator

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If a RST pin is available (AT3/AP2), you can use this to reset ANT, instead of the synchronous reset sequence involving SMRGDY and SRDY. This sequence is still available for backwards compatibility, but using just RST would be simpler.

On the same figure, I don't really understand the meaning of the spire between SEN and SRDY after the reset sequence.

After sending the reset, SEN will rise, and then go low. You must wait for the falling edge on SEN to pulse SRDY.

I've tied SFLOW and PORTSEL (pins 2 and 3) to High, but what do I have to do with IOSEL, BR2 and BR3 (pins 1, 4 and 5)?

SFLOW should be tied to low for byte synchronous communication, and high for bit synchronous.
BR2 and BR3 are not used, you can tie them to ground. IOSEL/RTS/SEN is a serial communication line. If you have IOSEL tied to ground that would explain why SEN always stays low; in the battery board, connect it to Vcc (the board has a weak pull up).

06 April 2010 09:55 AM #8

lgautier Newbie

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I've made a new state machine with all the advices you gave me, but there're still problems.
SEN is ok, but SCLK stay low even when I reset the chip with the reset button of the battery board. And I have the same result with the 2 chips of my dev-kit.

On the battery board, I've tied low SFLOW / BR2 / BR3 and tied up IOSEL and PORTSEL. I've added a pull up resistance on the SEN line and tie SIN high.

I can get any scope capture, I can only debugging with 4 lEDs :(
For now, I just want to get the sync byte, I'm not trying to transfert any command.

Do you have any idea, why SCLK stay low? [img size=580]http://www.thisisant.com/images/fbfiles/images/ANT_SSI_state_machine.png[/img]

06 April 2010 05:14 PM #9

alejandra Moderator

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The SRDY pulse in the state machine does not seem right - a pulse going low then high is what is required to generate the clock.

If you are still having issues, it would be really helpful to obtain scope captures of the reset sequence along with the start of the first transaction to see what is happening with the serial lines. You would need to verify that your lines do look like Fig. 3-2 of the Interfacing document and that the timing is correct.

11 June 2010 07:48 AM #10

lgautier Newbie

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Joined 2010-01-29

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Hi,

I obtained scope capture.
When I tie IOSEL, PORTSEL and SFLOW to High and BR2, BR3 to Low on my battery board, SCLK is set to '0', is it normal?
In my scope you can see that SRDY is low during 346us while SMSGRDY is High. But when SMSGRDY changes its state, SEN doesn't go down.

Any ideas?

Regards,
Lionel.

11 June 2010 07:52 AM #11

lgautier Newbie

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Here is my scope capture:

11 June 2010 07:53 AM #12

lgautier Newbie

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Joined 2010-01-29

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Here is my scope: [img size=596]http://www.thisisant.com/images/fbfiles/images/SSI_Scope.jpg[/img]

Time between T and X : 346 us
Time between X and Y : 1,38 ms

11 June 2010 09:14 AM #13

alejandra Moderator

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After the synchronous serial port is initialized successfully, SCLK will stay HIGH while waiting for the host to pulse SRDY. However, from the scope captures, it looks like you are never seeing SEN getting asserted, so the reset is not completing properly. Does the same thing happen if you issue the reset using the RESET pin?

You are still using the battery board, correct? Since there have been many modifications to your design, would you mind posting your current schematics for double checking?

11 June 2010 10:59 AM #14

lgautier Newbie

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I'm going to try using rst pin.
What should be the state of SMSGRDY and SRDY during the reset? Low?

11 June 2010 01:14 PM #15

alejandra Moderator

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Joined 2012-10-09

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The RESET pin is independent from SRDY/SMSGRDY, so it should not matter.

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