ANT Forum

Is it normal that I must have SIN tie High to get SEN low?

After a reset (using the reset button on the battery board) :
- SEN starts to pulse then stay low.
- SCLK is low.
- SIN is High.      

No, SIN is a serial data line, and should not be kept tied to low/high. There is probably something wrong in one of your connections. Could you post your current schematics?      

Configuration of dipswitches of my battery board:
1 - Vcc
2 - Vcc
3 - Vcc
4 - GND
5 - GND

SRDY is low during the reset then goes high.
SCLK stays low. [img size=461]http://www.thisisant.com/images/fbfiles/images/Schematic.png[/img]      

Is the pull-up resistor on SEN the one in the battery board, or is it an external pull-up? The battery board already has a pull-up on this line (all the lines connected to the DIP switch have one), so you do not really need it. You should not need to set your HOST_SOUT to high during initialization. As you are using the DIP switch to set SFLOW and PORTSEL to high, you do not really need to connect them to your MCU as well, unless you want to control the lines through software.

Are you driving the RESET pin for ANT from the RESET button on the battery board, or from an output on your MCU? Is it connected to the RESET pin at your MCU as well? Since some of the pins in your schematics are set by software rather than hardware (e.g. SFLOW, PORTSEL), they might be in an unknown state while your MCU is initializing, resulting in this odd behavior. If you intend to configure this lines by software, make sure that your MCU has been initialized and these lines are in a known state before you attempt to reset ANT.      

In fact, I'm using a FPGA to control the ANT device, so I have no unknown state.

What are the possible reason for SCLK to stay low (wrong switch, pull-up missing, ...)?
Isn't it suppose to be high as soon as the board is powered, changing state just during data transfer?      

Lines like SCLK, SOUT, SEN are configured by ANT depending on the serial mode configuration. SCLK for example is an input (BR2) if configured as UART and an output if configured in synchronous mode. Until the reset is complete, its state is undefined - there is a settling time from power up until the lines get configured as outputs/inputs and initialized when applying the reset. An FPGA will also have a settling time when you configure your lines, so you do have to consider this in your design if you are resetting both at the same time. Is the FPGA handling all your application, or just the ANT module?

Also, noticed that you set BR2/SCLK in the dip switch to GND. That would definitely pull it low. If you still have issues with incorrect line states, I would suspect a short, an incorrect pull-up or unintended coupling in your lines.      

Hi,

I've plugged directly my HOst to the ant module, without using the battery board and it's working perfectly.
I also think that the problem comes from my dip switches. On the battery board dip switch pinout there is BR1/SFLOW but not BR2/SCLK, it confused me.

Thank you for your help,
Lionel.