ANT Forum

Hello,
I am using a MSP430F2619 with the ANT AP2 module on the ANTAP2DK1 kit.
As far as I understand, on powerup, we can toggle the Reset hardware pin H-L-H for > 2.5us and then wait for >500ms and module should be synchronized and then the up can talk with it over SPI (byte sync mode)
This works well with AT3 module. However the AP2 module returns garbage (0x48) on reset. Can anyone tell me exact sequence to Reset the AP2 module upto the point where I can then tranmit ans set the network key command.
I have written code that works well with the AT3 module. It is just the AP2s that are an issue and I need to use AP2.

thank you.      

Hi,

What is the revision of the AP2 module you are using?

It should also be noted that AP2 modules send the startup message (0x6F) after power up/reset.      

Hello.
thank you for replying.

I am using Rev E of the AP2 surface mount modules.

What is exact sequence of synchronous reset ?

Do I need to assert-deassert (H-L-H) reset hardware pin after asserting SRDY, 250us delay, Asserting MRDY ?      

Hi,

Rev E of AP2 modules have a number of issues that are addressed in the Errata. Please do have a look at the errata (link below):
http://www.thisisant.com/images/Resources/PDF/ap2_rf_transceiver_module_errata.pdf

Since you are using the reset pin, you don't have to use the synchronous reset sequence. Using the reset pin method is easier compared to the synchronous reset sequence method.

Here are a couple of suggestions:

1) After power up/start up, wait for approximately 500 ms before reseting the module
2) After reset, wait for more than 500 ms then start sending messages to the module

If the suggestions above don't work, we would then need to see traces of the pins in order to solve the issue.      

Hello,

that reset sequence along with the 500ms wait on both occasions helped!

one issue i faced is that the reset sequence is not treated well in the documentation. no matter how simple it needs to be explained well with accurate timing diagram.

the other issue was that i had initialized the SPI module on program startup. On ANT reset, the module pulls the clock pin low and then high once. My msp430 interpreted this as one clock cycle and read 1 bit of data. then after 500ms, when the ANT module transmits the 0xA4 message, my SPI module read only the first 7 bits and thus i received garbage data. issue resolved courtesy logic analyzers!

thank you.