ANT Forum

I'm trying to implement byte sync mode with an AP2 and MSP430 host, in hardware.

After start up, I reset by pulsing the reset pin low for 10us, wait a few ms, bring down MRDY, check SEN, then pulse SRDY for 3us. The spi clocks come and I get a byte, but its not a sync byte. A simple scope capture of the SCLK and SOUT is below.

[img size=817]http://www.thisisant.com/images/fbfiles/images/myspi2.PNG[/img]

Since LSB is sent first, that is 0x6D? At this point there no commands have been sent or much of anything done, the module should be in a completely reset state.

This is using an AP2 module attached via the battery board. I doubled checked the dip switches to make sure they are setup for byte sync, 1(sen)-vcc 2(portsel)-gnd 3(sflow)-gnd 4(sclk)-vcc 5(br3)-gnd, where vcc is the vcc pullup from the battery board.

Any ideas what could cause that? Also, is it just me or does the clock phase and polarity not match the specs?      

PORTSEL needs to be connected to Vcc for synchronous communication.

In the AP2 module, after the reset, you should be getting a startup message, so your first transaction would be from ANT to the host MCU.      

PORTSEL is Vcc, I copied it to post wrong. So that's not it.

Even if the first message is from the ANT, I should still get a sync byte right? Either 0xA5 or 0xA4, so I don't know what the byte I get means.      

Yes, you should get a sync byte (0xA4). Could you capture what happens before this, after you do the reset (SEN, SRDY, MRDY and CLK)?      

Hello!

I also use SPI with byteflow with SS controlled by HW and SRDY is a normal output. I tried to do the Synchronisation like in "Interfacing ANT and General Purpose µC" fig.3-2 but I don't receive a writeflag 0xA5(write from the view of µC) eventhough MSGRDY,SEN,SRDY do the right thing to start writing to the ANT-Module(AP2). I always get 0xA4. So I decided to take a look if ANT is transmitting something else. I receive 0x81. I don't know what that means...

Here the steps I do:

Kind of connect-function:
1. set up SPI
2. PORTSEL=1 SFLOW=0 RESET=1 SRDY=1 MSGRDY=1
3. wait(300µs)
4. RESET = 0
5. wait(300µs)
6. RESET = 1 //reset done
7. wait(>2ms)
8. enable SPI

Next function is for synchronisation upon start-up:
9. SDRY=0
10. wait(300µs)
11. MSGRDY=0 // synchronisatio/reset done
12. wait for SEN=0
13. (*) wait(300µs)
14. SRDY=1

Function is for transmitting a message to ANT-Module:
15. MSGRDY=0 //since synchronisation (step 11.)
16. check SEN=0
17. SRDY=0 for more than 2.8µs than SRDY=1 // "readypulse()"
18. Read SPIBUF if ready
19. if(sync != 0xA5)return -1; // wrong sync!
20. ...
21. ...

(*) I don't know what in fig.3-2 the manual wants to tell me with the arroow fromSEN to SRDY:
Can I set SRDY to 0 immediately or should there be a delay?

Other questions I have:
When I reset the ANT-Module by using the pin, is there still a need for the Sychronisation upon start-up?

Hopefully someone can help me! Thank you in anticipation!

Best regards,

Matthias      

Hi Matthias,

In regards to the arrow in figure 3-2 of the "interfacing with ant..." document, it just means that the SRDY transition must come after the SEN transition. There is no specified time period, it just must be after.

As for the reset pin, if you initiate a reset via this pin, it will effectively apply the synchronization sequence, therefore it does not need to be applied again. It is also best practice is to send the software reset command after doing this to ensure that the ANT chip is in a known state (if the command is successful you know the communication is working).      

Thank you jefferson!

So the way I want to set up is okay and I will not make any unnecessary delays. But why do I receive no WR-Flag so that I can configure the ANT-Module? MSGRDY is still pulled down after SW-synchronisation and also SEN (or HOST_EN) is still pulled down. Next step is my "readyPulse()" where SRDY is pulled down for ca. 2.8µs. I don't know where I made a mistake? What can/should I try next?

Greets,
Matthias      

...
I measured with a scope that my ANT-AP2-Module starts clocking eventhough SRDY is high! I do the steps like in fig 3-2 (I hope so ). That must not happen. Can someone please give me an advice?

Best regards,
Matthias      

The problem was that Fig. 3-2 (Interfacing ANT & GPµC) is not telling everything, because it depends on the device: some send after reset and/or start-up. Therefore the first flag was a RD-Flag. I think the sixth Byte I received was the WR-Flag...
In the 'Message & Protocol'-man there was this mentioned.

BR