You are here: Forum Home → ANT Developer’s Forums → ANT General Questions → Thread
a) AP1, AP2 have asterisks at Power State row, but I found no explanation. "Forces Reset" sounds irrelevant
b) row SLEEP seems confusing in Table 2 and Table 3. Isn't better to name it BASE current in SLEEP state (as module datasheet does)?
c) Is info, that AT3/AP2 in ACTIVE state universally consumes current in units of mA, correct? Why there is no such important info in datasheet(s), where on the beginning can be read "Ultra low power operation"?
When I power up AT3 module and perform reset by toggling RESET line (in ACTIVE state now, according to Figure 1., RTS pulse correctly obtained), AT3 module draws only ~2,3uA (in contrast of a given value in Table 2. Farther when SLEEP line is 1, current is lowered to 0,9uA, i.e. SLEEP state).
But when I do the same process with AP2 (+ Startup message A4 01 6f 01 CB ... RESET line (0x01) received), it really consumes about 2,5mA. How to understand this difference? It looks like AT3 goes to UNKNOWN low power state automatically (but "ANT will automatically transition to the IDLE state" is mentioned only for SYNC interface), but AP2 don't ("On start-up or after a reset, ANT will be in the ACTIVE state"), both with SLEEP line hold low, SUSPEND high and with no one serial message (not even 1 channel assigned).
2. a) Why is transition from ACTIVE to DEEP SLEEP state described only with serial message Deep_Sleep_Cmd (AN13/ Figure 1.)?
Isn't correct to paint Deep_Sleep_Cmd & (Goto_Sleep within 1.2ms)?
Also transition from DEEP SLEEP to IDLE with forcing reset is missing: Deep_Sleep_Cmd & !(Goto_Sleep within 1.2ms)
b) Presumptions:
- ASYNC interface, AP2 revision E
- Startup message correctly obtained (message A4 01 6f 01 CB ... RESET line (0x01) received)
It is strange, but I cannot enter into DEEP SLEEP state with AP2 revision E using this mechanism (1.2 ms kept).
Module still draws 2,4uA (that corresponds to SLEEP state current, so absolute minimum 0,5uA is disqualified)
3.Presumptions:
- ASYNC interface, AP2 revision E
- AP2 datasheet lists feature: On board 32.768 kHz crystal oscillator
and note 8) says "Value calculated assuming the onboard 32.768 kHz crystal oscillator is enabled. The ANT_CrystalEnable() message must be used to enable this clock source.
- forum writes: The AP2 defaults to the internal RC clock which is very fast compared to an external clock, but testing the external crystal on an AP2 module revealed very fast startup times as well.
By using the external crystal the base current draw may be low enough for your application, and using byte synchronous SPI if possible will also lower your current consumption for the AP2.
If current consumption on the AP2 still would not be acceptable, the AT3 chipset should also give the latency requirement you need at a lower active current than the AP2 but this has not been tested.
When I observe current consumption in SLEEP state, I cannot see any current diference no matter if I send Crystal Enable (Startup notification message and following RESPONSE_NO_ERROR message for command 0x6D correctly obtained) serial message OR not.
Difference should be 84uA(nRFAP2)/97uA(AN13) in base current (87uA x 3uA)/(100uA x 3uA). Or not?
So, isn't 32.768kHz oscillator for AP2 enabled by default? ANT_CrystalEnable() message then shouldn't be necessary.
4. AP2 datasheet says:
a) "pin compatible with ANT AP1 and AT3 modules"
b) Surface Mount Pins 5 and 8 are NC (No connection)
Couldn't be (possibly in future improvement/SPECIAL TEST modes of module AP2) some troubles, when we left these 2 pins tied to GND (to have designed PCB compatible for AP2 and also AT3)?
Or these pins MUST be strictly left unconnected as depicted?
1. AN13: ASYNC mode/Table 2 and Table 3.
a) AP1, AP2 have asterisks at Power State row, but I found no explanation. "Forces Reset" sounds irrelevant
Looks like a typo. Thanks for pointing this out. The asterisk refers to the text below: for AP1/AP2, ANT will not traverse through this states automatically.
c) Is info, that AT3/AP2 in ACTIVE state universally consumes current in units of mA, correct? Why there is no such important info in datasheet(s), where on the beginning can be read "Ultra low power operation"?
While instantaneous current consumption can be in the range of mA, this is only for very short periods of time. In average the consumption is in uA.
When I power up AT3 module and perform reset by toggling RESET line (in ACTIVE state now, according to Figure 1., RTS pulse correctly obtained), AT3 module draws only ~2,3uA (in contrast of a given value in Table 2. Farther when SLEEP line is 1, current is lowered to 0,9uA, i.e. SLEEP state).
But when I do the same process with AP2 (+ Startup message A4 01 6f 01 CB ... RESET line (0x01) received), it really consumes about 2,5mA. How to understand this difference? It looks like AT3 goes to UNKNOWN low power state automatically (but "ANT will automatically transition to the IDLE state" is mentioned only for SYNC interface), but AP2 don't ("On start-up or after a reset, ANT will be in the ACTIVE state"), both with SLEEP line hold low, SUSPEND high and with no one serial message (not even 1 channel assigned).
AT3 is the only part where ANT handles power states transitions automatically. For AP2, you do need to use the SLEEP/SUSPEND lines to get it to reach its lowest power state.
b) Presumptions:
- ASYNC interface, AP2 revision E
- Startup message correctly obtained (message A4 01 6f 01 CB ... RESET line (0x01) received)
It is strange, but I cannot enter into DEEP SLEEP state with AP2 revision E using this mechanism (1.2 ms kept).
Module still draws 2,4uA (that corresponds to SLEEP state current, so absolute minimum 0,5uA is disqualified)
Please refer to the AP2 Module revision history (you'll find it right below to the datasheet). A module level fix for the "Supply Voltage Issue" (3.13) was implemented in module rev E. This fix removes the Deep Sleep Mode. I can see how the current consumption table there is confusing - we'll need to fix that.
3.Presumptions:
- ASYNC interface, AP2 revision E
- AP2 datasheet lists feature: On board 32.768 kHz crystal oscillator
and note 8) says "Value calculated assuming the onboard 32.768 kHz crystal oscillator is enabled. The ANT_CrystalEnable() message must be used to enable this clock source.
- forum writes: The AP2 defaults to the internal RC clock which is very fast compared to an external clock, but testing the external crystal on an AP2 module revealed very fast startup times as well.
By using the external crystal the base current draw may be low enough for your application, and using byte synchronous SPI if possible will also lower your current consumption for the AP2.
If current consumption on the AP2 still would not be acceptable, the AT3 chipset should also give the latency requirement you need at a lower active current than the AP2 but this has not been tested.
When I observe current consumption in SLEEP state, I cannot see any current diference no matter if I send Crystal Enable (Startup notification message and following RESPONSE_NO_ERROR message for command 0x6D correctly obtained) serial message OR not.
Difference should be 84uA(nRFAP2)/97uA(AN13) in base current (87uA x 3uA)/(100uA x 3uA). Or not?
So, isn't 32.768kHz oscillator for AP2 enabled by default? ANT_CrystalEnable() message then shouldn't be necessary.
The fix for the issue above for module Rev E involved enabling the crystal by default. However, sending the command will not produce any ill effects, so it is recommended to still use the command for firmware compatibility with other module revs.
